MPW Semiconductor Runs Explained: From First Silicon to Engineering Sample Distribution
- info1931301
- Mar 25
- 6 min read
Updated: Mar 28
An MPW (Multi-Project Wafer) run allows multiple semiconductor designs to share a single wafer, reducing costs and enabling fabless companies to produce first silicon (A0) without full production investment. After fabrication and packaging, these chips are delivered as engineering samples, which must be carefully tracked, managed, and distributed for testing and validation.
MPW Semiconductor Workflow: From Fabless Design to OSAT-Packaged Engineering Samples.
This diagram illustrates the MPW (multi-project wafer) process, where multiple fabless semiconductor companies combine designs into a shared wafer, which is fabricated by a foundry and then packaged by an OSAT provider into A0 engineering samples for validation and testing.
Learn more about MPW semiconductor runs and first silicon distribution here:
What Is an MPW Run of Semiconductors?
An MPW (multi-project wafer) run is a semiconductor manufacturing process where multiple chip designs share a single wafer, reducing cost and enabling companies to produce first silicon (A0) for testing and validation.
An MPW (Multi-Project Wafer) run is a shared manufacturing process where multiple chip designs are fabricated on a single wafer.
After tapeout, designs enter fabrication at a foundry such as TSMC, Global Foundaries or similar advanced-node, mature, or specialty providers.
Instead of paying for an entire wafer, each company:
contributes a portion of the design
shares fabrication costs
receives a smaller quantity of chips
This makes MPW runs ideal for:
startups
university research
early-stage product development
What Is First Silicon (A0) and Why It Matters
First silicon—commonly referred to as A0—is the first physical version of a chip produced after tapeout and fabrication. It represents the moment a design moves from simulation to reality.
At this stage, the chip has never been tested in the real world. While simulations and verification catch many issues, A0 silicon is where actual performance, edge cases, and unexpected behavior begin to surface.
Validation Starts Here
A0 silicon is used for initial validation, where engineering teams confirm:
core functionality
electrical performance
power characteristics
interface behavior
This phase determines whether the design works as intended—or needs revision.
Debugging Drives Iteration
It’s expected that A0 silicon will reveal issues.
Teams use these early samples to:
identify design flaws
isolate failure modes
validate fixes
These findings inform the next revision (B0, C0, etc.), making accurate tracking of which silicon is being tested critical.
Distribution Enables Progress
A0 silicon is not just tested in one place—it’s distributed to:
internal engineering teams
OEM partners
validation labs
early customers
Each group may be testing different use cases, environments, or system integrations.
That means:
the right silicon must reach the right people
revisions must be clearly identified
lot and batch traceability must be maintained
Why This Stage Is Critical
This is where momentum is either gained—or lost.
If A0 samples are:
delayed → validation slows
misidentified → debugging becomes unreliable
poorly tracked → results become difficult to trust
First silicon isn’t just a milestone—it’s the foundation for everything that follows.
And how it’s managed, tracked, and distributed directly impacts how quickly a company moves from prototype to production.
How Shared Wafers Work
In an MPW run, designs from multiple companies are combined onto one wafer layout.
The typical post-tapeout flow:
Wafer Fabrication (6–12 weeks typical)
Multi-project wafer (MPW) runs combine multiple designs
Process node and queue time impact delivery
Wafer Sort / Probe Testing
Electrical testing at wafer level
Identification of known-good dies (KGD)
Assembly & Packaging (OSAT)
Handled by providers like ASE Group
Includes die singulation, wire bonding / flip chip, encapsulation
Final Test & Binning
Functional validation
Speed / performance grading
Engineering Sample Release
A0 silicon (first revision)
Follow-on B0 revisions after fixes
What Makes Engineering Samples Operationally Different
Engineering samples are not standard inventory.
They differ from production units in several critical ways:
Low volume, high value: Often tens to hundreds of units
Revision-sensitive: A0 vs B0 must never be mixed
Time-critical: Delays directly impact validation cycles
Non-repeatable: Lost units cannot be quickly replaced
Unlike production logistics, where redundancy exists, engineering sample logistics operates under scarcity constraints.
Failure Points in Engineering Sample Logistics
Most semiconductor teams do not design logistics systems for this phase, leading to predictable breakdowns.
1. Lack of Lot & Revision Control
Without structured inventory systems, teams rely on spreadsheets or ad hoc tracking.
This creates risk of:
Mixing A0 and B0 revisions
Losing traceability of test results
Shipping incorrect units to stakeholders
Standards from organizations like SEMI emphasize traceability across the semiconductor supply chain.
2. Fragmented Distribution
Engineering samples are typically distributed across:
Internal validation labs
Firmware/software teams
External test houses
Early customers or design partners
Each requires:
Different quantities
Specific labeling
Controlled delivery timelines
Without a centralized fulfillment process, distribution becomes inconsistent and difficult to audit.
3. Improper Handling & Packaging
Semiconductor devices require controlled handling:
Moisture barrier bags (MSL compliance where applicable)
Shock protection
Failure here can invalidate test results or damage units before they are even evaluated.
Damaged units from Electrostatic Discharge (ESD) is something large corporate fulfillment centers simply aren't equipped to prevent.
4. No System for Shipment Tracking
Shipping engineering samples is not just about delivery—it’s about visibility.
Teams need to know:
Where each unit was sent
When it was delivered
Which revision was tested by which stakeholder
Without this, debugging issues across teams becomes significantly harder.
Building a Structured Engineering Sample Logistics System
To support rapid iteration cycles, logistics must be treated as a controlled system—not an afterthought. This is where MPW providers and ASIC often assume unnecessary risk or place the burden of logistics back onto their fabless semiconductor startups.
Receiving & Intake
Validate incoming quantities from OSAT
Record lot numbers, wafer IDs, and revisions
Inspect packaging condition
It's a critical yet overlooked handover of logistics. At this point ASICs and MPWs can make two critical errors with successfully forged engineering samples. Either placing responsibility on a 3PL who doesn't appreciate the sensitivity of the commodity they are receiving and handling, or leveraging their own staff who's bandwidth can be better used elsewhere and can't operate with the speed of a logistics professional.
Inventory & Traceability
A proper system should track:
Lot / batch number
Revision (A0, B0, etc.)
Quantity available
Allocation status
This allows teams to correlate test results directly to specific silicon batches.
Order Fulfillment & Allocation
Instead of ad hoc shipments, use structured fulfillment:
Allocate samples by project or team
Pick and pack by lot and revision
Include documentation or labeling as required
Shipping & Carrier Optimization
Engineering samples often require:
Expedited shipping (Next Day / International Express)
Customs documentation for cross-border movement
Carrier selection based on reliability and speed
Why This Stage Is Often Outsourced
Fabless semiconductor companies are optimized for design—not logistics execution.
As a result, internal teams often:
Spend engineering time managing shipments
Lack systems for traceability
Experience delays between validation cycles
By outsourcing engineering sample fulfillment, teams can:
Maintain structured inventory control
Ensure consistent distribution workflows
Reduce operational overhead
Accelerate iteration cycles between A0 and B0
Engineering Sample Fulfillment for Semiconductor Teams
Fulfillment CO supports semiconductor companies during the post-tapeout phase by providing structured logistics for engineering samples.
This includes:
Receiving samples from OSAT providers
Lot and revision tracking
Controlled pick, pack, and distribution
Domestic and international shipping coordination
The goal is simple: Ensure engineering samples move efficiently between stakeholders without introducing delays or errors.
Frequently Asked Questions
What is an MPW run?
A multi-project wafer (MPW) run allows multiple chip designs to share a single wafer, reducing cost during early-stage development.
What are A0 vs B0 samples?
A0 represents first silicon after tapeout. B0 includes revisions based on issues discovered during A0 validation.
Why are logistics critical after tapeout?
Because engineering samples are limited and time-sensitive. Poor logistics can delay validation, debugging, and customer engagement. Poor logisticians likely underappreciate the detail orientation and care for chips amid a fulfillment environment mired in other non-specialized products.
Final Thoughts
The transition from tapeout to validation is not just a technical process—it’s an operational one.
Teams that treat engineering sample logistics as a structured system gain:
Faster validation cycles
Better traceability
Fewer delays between revisions
Those that don’t often find themselves slowed down not by silicon—but by the movement of that silicon.
If you're managing engineering samples after an MPW run, outsourcing to a 3PL who can appreciate your product and structure a workflow that can be adapted to your ideal service cycle system will remove a major source of friction from your development cycle and that of your clients. This ensures you retain fabless semiconductor companies and institutions' trust and repeat business.
